A new programmable probabilistic computer has been developed using 1 million p-bits, overcoming previous limitations of single-chip systems. This architecture allows for faster Gibbs sampling while maintaining on-chip memory for coupling weights, presenting significant advancements for hardware accelerators in probabilistic computing.
The recent advancement in programmable probabilistic computing has led to the creation of a system capable of utilizing 1 million p-bits. This development marks a significant enhancement over traditional single-chip systems that have limited capacity and memory bandwidth. By networking field-programmable gate arrays (FPGAs), researchers successfully created a larger Ising machine that expands computational potential beyond previous constraints.
The newly developed machine performs Gibbs sampling at an impressive rate of over one trillion flips per second. A key feature is that it keeps every coupling weight in local on-chip memory, enabling efficient processing and reducing latency. During its operations, devices only exchange 1-bit boundary states, streamlining the communication process between devices.
The study revealed a fundamental question regarding boundary information exchange rates for partitioned machines. A single timing ratio, defined as eta = f_comm/f_p-bit, indicates the boundary-exchange frequency related to the local p-bit update frequency. Results show that above a certain topology-dependent threshold, the performance aligns with that of monolithic GPU references. However, when below that threshold, a power-law decay in residual energy affects performance, presenting a tradeoff between throughput and accuracy.
This platform has demonstrated its effectiveness using three-dimensional Edwards-Anderson spin glasses, Max-Cut, and Boolean satisfiability problems. The researchers also introduced a theoretical cluster mean-field model, which matches the observed behaviors, signifying a universal characteristic of partitioned stochastic dynamics. These findings suggest a clear path for scaling probabilistic computers beyond the constraints of single-chip architectures.
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A new programmable probabilistic computer has been developed using 1 million p-bits, overcoming previous limitations of single-chip systems. This architecture allows for faster Gibbs sampling while maintaining on-chip memory for coupling weights, presenting significant advancements for hardware accelerators in probabilistic computing.